Synopsys Kicks Off ITC 2014 Activities with Test SIG Event Featuring Semiconductor Leaders Sharing Insights on Newest Silicon Test Technologies!

Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, will showcase advances in its comprehensive synthesis-based test solution during the International Test Conference (ITC) 2014 in Seattle Washington. Kick off the conference by joining Synopsys at its annual Test Special Interest Group (SIG) event, hear a plenary keynote speech from Synopsys Chairman and co-CEO Dr. Aart de Geus, and attend numerous technology sessions featuring Synopsys test experts throughout the three-day conference.

Synopsys_Logo_It VoiceFor detailed information about all Synopsys activities at ITC, including the Test SIG event, please visit: http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/itc-2014.aspx.

To register for the Test SIG event, please visit: http://www.synopsys.com/cgi-bin/testsig14/reg1.cgi.

What: Test SIG 2014 Event
Topic: The latest silicon test technologies
When: Monday, 10/20, 6:30 p.m. – 9:30 p.m.
Where: ITC 2014, Metropolitan Ballroom, Sheraton Seattle Hotel, Seattle, Washington
Description: Test experts from leading semiconductor companies and foundries will discuss the latest in silicon test technologies and share their experiences and insights on how to achieve higher test quality and lower test cost, faster.Topics to be discussed include: new fault models for emerging process nodes and FinFETs, new compression technologies, latest diagnostic techniques and advanced memory test and repair.

Dr. de Geus will welcome attendees, experts will present, and a question and answer session will follow each presentation for direct speaker-audience interaction. During this dinner event, attendees will have the opportunity to talk with industry peers and the Synopsys test research and development staff. This event is open to all IC designers, managers and members of the media interested in increasing test quality and reducing test cost.

Synopsys Exhibit (Booth #511)
Tuesday, 10/21, 10:30 a.m. – 5:30 p.m.
Wednesday, 10/22, 9:30 a.m. – 5:00 p.m.
Thursday, 10/23, 9:30 a.m. – 1:00 p.m.

Come learn about the latest innovations in Synopsys’ test solution for achieving higher defect coverage, higher compression, faster yield learning and improved life-cycle reliability.

Opening Plenary Keynote: Testing Positive… for Complexity

Tuesday, 10/21, 9:00 a.m. – 10:30 a.m.
Dr. Aart de Geus, chairman and co-CEO, Synopsys

Multiple Paper Presentations and Panels
Synopsys test experts will participate in a number of technical sessions, panels and workshops within the ITC 2014 program. These activities will cover a broad array of test-related topics, with a particular focus on achieving higher defect overage, compression and life-cycle reliability.

For a comprehensive list of Synopsys activities at ITC, please visit: http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/itc-2014.aspx

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