At the 2013 International Test Conference, GOEPEL electronic introduced an Automatic Application Program Generators (AAPG) for design validation and test of FPGA integrated high-speed I/O (HSIO) based on the ChipVORX® technology for FPGA Embedded Instruments. Users can now evaluate transmission channel quality by utilizing Bit Error Rate Tests (BERT). This provides a graphical evaluation per dynamic eye diagram to support design validation.
The development towards FPGA based board designs is also accompanied by more and more high-speed I/O, difficult to test by traditional metrology due to continuously decreasing physical access. Our new solution addresses this very problem”, says Heiko Ehrenberg, Technology Officer for Embedded System Access for GOEPEL electronics in the USA. “Because of high automation level, the high-speed I/O’s FPGA parameters can be interactively defined, and become immediately effective without design synthesis, i.e. users can directly validate the influence on transfer quality. Furthermore, signals received in the silicon are recorded and visualized, which enables unaltered measurement results.
