AMD has announced a major breakthrough in high-performance computing (HPC) with the successful tape-out and bring-up of its next-generation EPYC™ processor, codenamed “Venice,” built on TSMC’s cutting-edge 2nm (N2) process technology. This achievement makes it the first industry HPC product to reach this milestone on TSMC’s N2 node, showcasing the strong collaboration between AMD and TSMC in co-optimizing advanced design architectures and semiconductor manufacturing.
The upcoming “Venice” processor is set to launch next year and represents a significant advancement in AMD’s data center CPU roadmap. Additionally, AMD has confirmed the successful validation of its 5th Gen EPYC™ CPUs at TSMC’s new Arizona-based fabrication facility, reinforcing AMD’s commitment to supporting U.S. semiconductor manufacturing.
Dr. Lisa Su, Chair and CEO of AMD, emphasized the long-standing partnership with TSMC, stating that their close collaboration has consistently delivered leadership products in high-performance computing. She highlighted AMD’s role as a lead HPC customer for both the TSMC N2 process and the Arizona Fab 21 as examples of innovation-driven teamwork.
Dr. C.C. Wei, Chairman and CEO of TSMC, expressed pride in having AMD as a lead customer for its most advanced technologies. He noted that this partnership is driving key advancements in performance, power efficiency, and silicon yield, setting the stage for the next era of computing.
