256 Gigabit 3-Bits-Per-Cell Chip is the Smallest in the Industry
Western Digital Corp. today announced that it has successfully developed its next generation 3D NAND technology, BiCS3, with 64 layers of vertical storage capability. Pilot production of the new technology has commenced in the Yokkaichi, Japan joint venture facilities and initial output is expected later this year. Western Digital expects meaningful commercial volumes of BiCS3 in the first half of calendar 2017.
“The launch of the next generation 3D NAND technology based on our industry-leading 64 layer architecture reinforces our leadership in NAND flash technology,” said Dr. Siva Sivaram, executive vice president, memory technology, Western Digital. “BiCS3 will feature the use of 3-bits-per-cell technology along with advances in high aspect ratio semiconductor processing to deliver higher capacity, superior performance and reliability at an attractive cost. Together with BiCS2, our 3D NAND portfolio has broadened significantly, enhancing our ability to address a full spectrum of customer applications in retail, mobile and data center.”
BiCS3, which has been developed jointly with Western Digital’s technology and manufacturing partner Toshiba, will be initially deployed in 256 gigabit capacity and will be available in a range of capacities up to half a terabit on a single chip. Western Digital expects volume shipments of BiCS3 for the retail market in the fourth calendar quarter of 2016 and to begin OEM sampling this quarter. Shipments of the company’s previous generation 3D NAND technology, BiCS2, continue to customers in retail and OEM.